1. Field of the Invention
The present invention is related to a method of calibrating signal skews and related transmission system, and more particular, to a method of calibrating signal skews in MIPI (mobile industry processor interface) and related transmission system.
2. Description of the Prior Art
With rapid development in technology, high-speed serial transmission technology had been used in electronic devices for providing larger data throughput. Such transmission technologies include MIPI (mobile industry processor interface), MDDI (mobile display digital interface), or USB (universal serial bus), etc. Among them, MIPI technology has been widely used in mobile devices including smart phones or PDAs (personal digital assistants) and can provide adjustable data rate using a differential clock lane and expandable (1˜4) data lanes.
FIG. 1 is a diagram illustrating a prior art transmission system 10. The transmission system 10 adopts 4-channel MIPI and includes a host side circuit HS, transmission lanes 200˜204, and a client side circuit CS. The host side circuit HS includes transmitting circuits 110˜114 respectively configured to transmit a clock signal CLK and data signals DATA1˜DATA4. The client side circuit CS includes receiving circuits 310˜314 respectively configured to receive the clock signal CLK and the data signals DATA1˜DATA4. The clock signal CLK and the data signals DATA1˜DATA4 may be transmitted from the transmitting circuits 110˜114 to the receiving circuits 310˜314 via the transmission lanes 200˜204, respectively.
FIGS. 2A˜2D are signal diagrams illustrating the operation of the prior art transmission system 10. The waveforms of the clock signal CLK and the data signals DATA1˜DATA4 are depicted. The client side circuit CS is configured to latch the data signals DATA1˜DATA4 at the rising or falling edge of the clock signal CLK. A setup time TS is defined as the shortest time between the rising edges of the clock signal CLK and the data signals DATA1˜DATA4, or between the falling edges of the clock signal CLK and the data signals DATA1˜DATA4. A hold time TH is defined as the shortest time between the rising edge of the clock signal CLK and the falling edge of the data signals DATA1˜DATA4, or between the falling edge of the clock signal CLK and the rising edge of the data signals DATA1˜DATA4.
In the ideal situation, the clock signal CLK and the data signal DATA1 are balanced in phase (TS=TH), as depicted in FIG. 2A. However in real applications, signal skew may be present in MIDI due to unmatched length/loading of the transmission lanes 200˜204, unmatched output of the transmitting circuits 110˜114, unmatched loading of the receiving circuits 310˜314, or discontinuous impedance between the host side circuit HS and the client side circuit CS. Therefore, the clock signal CLK and the data signals DATA1˜DATA4 may not arrive at the client side circuit CS simultaneously. For example, the clock signal CLK may lead the data signal DATA2 in phase (TS<TH), as depicted in FIG. 2B; the clock signal CLK may lag the data signal DATA3 in phase (TS>TH), as depicted in FIG. 2C; the phase difference between the clock signal CLK and the data signal DATA4 may exceed a unit period UI (TS<0), as depicted in FIG. 2D.
In real applications, MIPI normally includes a plurality of transmission lanes which may cause different amount of signal delays. As the operating frequency increases, the margin of error for signal skew (setup time TS and hold time TH) become narrowed, thereby reducing data accuracy. Therefore, there is need for a method capable of calibrating signal skew in MIPI in order to maintain the accuracy of data transmission.